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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-27204-3E
ASSP
SWITCHING REGULATOR CONTROLLER
MB3775
LOW VOLTAGE DUAL PWM SWITCHING REGULATOR CONTROLLER
The MB3775 is a dual pulse-width-modulation control circuit. It contains the basic circuits required for two PWM control circuits. Complete synchronization is obtained by using the same oscillator output waveform. This IC can provide following types of output voltage: step down, step up, and inverter. Power consumption is low, thus the MB3775 is ideal for use in highefficiency portable equipment.
(DIP-16P-M04)
* * * * * * *
Wide supply voltage range: 3.6 V to 18 V Low current consumption: 1.3 mA typical Wide oscillation frequency range: 1 kHz to 500 kHz On-chip timer latch short protection circuit On-chip under voltage lockout protection On-chip reference voltage: 1.28 V Variable dead time provides control over total operating range. (Ta = 25C) Value 20 -0.3 to +10 20 75 Ta 25 C(SOP) Power Dissipation PD TOP Tstg Ta 25 C(DIP) Ta 25C(VSOP) *620 1000 *430 -30 to +85 Unit V V V mA mW mW mW C C
(FPT-16P-M06)
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating Power Supply Voltage Error Amp. Input Voltage Collector Output Voltage Collector Output Current Symbol VCC VI VO IO Condition
(FPT-16P-M05) PIN ASSIGNMENT (TOP VIEW)
CT RT +IN1 -IN1 FB1 D.T.C.1 OUT1 E/GND
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
Operating Temperature Storage temperature
-55 to+125
*: The packages are mounted on the epoxy board (4 cm x 4 cm x 1.5 mm) NOTE : Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VREF SCP +IN2 -IN2 FB2 D.T.C.2 OUT2 VCC
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
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BLOCK DIAGRAM
9
VCC 1.9V 1.3V -
1
2
VREF=1.28V
16
Reference Voltage 2.5V
Triangular Waveform + _ _ PWM Comp 1 + _ _ PWM Comp 2
OUT 1
7
3 4 5 12
Error Amp 1 + _
+ + _
S.C.P. Comp
OUT 2
10
1.1V 2.5V 1A S R R U.V.L.O. + + _ D.T.C. Comp 1.8V
6 11
Error Amp 2 + 14 _ 13
15
1.28V 0.9V 0.9V
Latch
8
GND
s
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VCC VI VO IO CP CT RT fOSC IREF TOP Value Min 3.6 -0.2 - 0.3 - 150 5.1 1 -3 -30 Typ 6.0 - - - 0.1 - - - -1 25 Max 18 1.45 18 50 - 15000 100 500 - 85 Unit V V V mA F pF k kHz mA C
Power Supply Voltage Error Amp. Input Voltage Collector Output Voltage Collector Output Current Phase Compensation Capacitor Timing Capacitor Timing Resistor Oscillator Frequency Reference Voltage Output Current Operating Temperature
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OPERATION DESCRIPTION
1. Reference voltage
The reference voltage circuit generates a stable, temperature-compensated 2.5 V reference from Vcc (pin 9) for use by internal circuits. A reference voltage of temperature compensated 1/2 Vref can be obtained to external circuit by Vref terminal (pin 16).
2. Oscillator
A triangular waveform of any frequency is obtained by connecting an external capacitor and resistor to the CT (pin 1) and RT terminals (pin 2). The amplitude of this waveform is from 1.3 V to 1.9 V. The oscillator is internally connected to the non-inverting inputs of the PWM comparators. The oscillator waveform is available at the CT terminal.
3. Error amplifiers
The error amplifier detects the output voltage of the switching regulator. The common-mode input voltage range is -0.2 V to 1.45 V, so the input reference voltage can be set the VREF and GND levels. Error amplifiers can be used as either inverting and non-inverting amplifiers. The voltage gain is fixed. Phase compensation is possible by connecting a capacitor to the FB terminals (pins 5 and 12) of the error amplifiers. The error amplifier output are internally connected to the inverting inputs of the PWM comparators and also to the short protection circuit.
4. Timer latch short protection circuit
The timer latch short protection circuit detects the output levels of the error amplifiers. If one or both error amplifier outputs are 1.1 V or lower, the timer circuit begins charging the externally connected protection enable capacitor. If the output level of the error amplifier does not drop below the normal voltage range before the capacitor voltage reaches the transistor base-emitter voltage VBE ( 0.65 V), the latch circuit turns the output drive transistor off and sets the dead time to 100 %.
5. Under voltage lockout protection circuit
An ambiguous transition state at power-on or a momentary fluctuation in the supply line may result in loss of control and may adversely affect or even destroy the system. The under voltage lockout protection circuit compares the internal reference voltage level with the supply voltage level. If the supply voltage level falls below the reference level the latch circuit is reset the output drive transistor is turned off and the dead time is set to 100 %. The protection enable terminal (pin 15) is pulled "Low".
6. PWM comparator
Each PWM comparator has two inverting inputs and one non-inverting input. This voltage-to-pulse-width converter controls the output pulse width according to the input voltage. The PWM comparator turns the output drive transistor on when the oscillator triangular waveform is higher than the error amplifier output and the dead time control terminal voltage.
7. Output drive transistor
The open-collector output-drive transistors provide common-emitter output of 18 V dielectric capability. The output drive transistors can source up to 50 mA of drive current to the switching power transistor.
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ELECTRICAL CHARACTERISTICS
(Ta=25C, VCC=6V) Parameter condition Symbol Value Min Typ Max Unit
Reference Section
Output Voltage Output Temp. Stability Input Stability Load Stability Short Circuit Output Current
Under Voltage Lockout Protection Section
IOR =-1 mA Ta = -30 C to +85 C VCC = 3.6 V to 18 V IOR = -0.1 mA to -1 mA VREF = 0 V
VREF VRTC Line Load IOS
1.26
1.28 0.2 2 1
1.30 2 10 7.5
V % mV mV mA
-2 - - -
-30
-10
Threshold Voltage Hysteresis Width Reset Voltage (VCC)
Protection Circuit Section
IOR = -0.1 mA IOR = -0.1 mA IOR = -0.1 mA
VtH VtL VHYS VR
- -
80 1.5
2.72 2.60 120 1.9
- - - -
V V mV V
Input Threshold Voltage Input Stand by Voltage Input Latch Voltage Input Source Current Comparator Threshold Voltage
Triangular Waveform Oscillator Section
VtPC
0.60
0.65 50 50 -1.0 1.1
0.7 100 100 -0.6
V mV mV A V
No pull up No pull up
VSTB VI Ibpc
- -
-1.4
Pin 5, Pin 12
VtC
-
-
Ocillator Frequency Frequency Deviation Frequency Stability (VCC) Frequency Stability (Ta)
Dead-Time Control Section
CT = 330 pF, RT = 15 k CT = 330 pF, RT = 15 k VCC = 3.6 V to 18 V Ta = -30 C to +85 C
fOSC fdev fdV fdT
- - - -4
200 10 1
- - -
4
kHz % % %
-
Input Threshold Voltage (fOSC = 10 kHz) Input Bias Current Latch Mode Source Current Latch Input Voltage
Duty Cycle = 0 % Duty Cycle = 100 %
Vt0 Vt100 Ibdt
-
0.2
1.0 0.4 -0.2 -150
VREF -0.15
V V A A V
- -1
-80
- -
VREF -0.1
Vdt = 0.7 V Idt=-40 A
Idt Vdt
-
-
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ELECTRICAL CHARACTERISTICS (Continued)
(Ta=25C, VCC=6V) Parameter Condition Symbol Value Min Typ Max Unit
Error Amp. Section
Input Offset Voltage Input Offset Current Input Bias Current Common Mode Input Voltage Range Voltage Gain Frequency Band Width Common Mode Rejection Ratio Max. Output Voltage Width Output Sink Current Output Source Current
PWM Comparator Section
VO = 1.6 V VO = 1.6 V VO = 1.6 V VCC=3.6V to 18V
VIO IIO IB VICR AV
-10 -100 -500 -0.2 84 - 60 2.2 - 24 -
- - -100 - 120 3 80 2.4 0.7 50 -1.2
+10 +100 - +1.45 - - - - 0.9 - -0.7
mV nA nA V V/V MHz dB V V A mA
AV = -3 dB
BW CMRR VOM+ VOM-
VO = 1.6 V VO = 1.6 V
IOM+ IOM-
Input Threshold Voltage (fOSC=10 kHz) Input Sink Current Input Source Current
Output Section
Duty Cycle = 0 % Duty Cycle = 100 %
Pin 5, Pin 12 = 1.6 V Pin 5, Pin 12 = 1.6 V
Vt0 Vt100 IIN+ IIN-
- 1.05 24 -
1.9 1.3 50 -1.2
2.1 - - -0.7
V V A mA
Output Leak Current Output Saturation Voltage
VO=18V IO=50 mA
Leak VSAT
- -
- 1.1
10 1.4
A V
Stand by Current Average Supply Current
Output "OFF" RT=15k
ICCS ICCa
- -
1.3 1.7
1.8 2.4
mA mA
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TEST CIRCUIT
INPUT TEST SW CPE 4.7k VCC=6V
OUTPUT 1 4.7k OUTPUT 2 16 15 14 13 12 11 10 9
MB3775 1 0.1 F 330pF 15k 2 3 4 5 6 7 8
TEST INPUT
s
TIMING CHART (Internal Waveform)
Error Amp. output Triangular waveform osillator output 1.9V Dead Time PWM 1.5V input voltage 1.3V Short circuit protection 1.1V comparator Reference input "High" PWM comparator output "Low" Output Transistor collector waveform S.C.P Terminal . waveform "High" "Low" 0.6V 0V tPE
LOCK-OUT
DEAD TIME 100%
Short circuit protection "High" comparator output "Low" LOCK-OUT CANCEL Power supply voltage 3.6V (VCC : Min. Value) 0V Protection Enable Time tPE 0.6 x 106 x CPE (sec) 2.8 V (Typ. Value)
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APPLICATION CIRCUIT
Fig. 1 - Chopper Type Step Down/Inverting VIN (10V) 820pF 1 10k 2 3 2.3k 4 5 33k +1F 33k +1F 5.6k 330 330 470 120H 9.1k V0- (-5V) Fig. 2 - Chopper Type Step Up/Inverting VIN (5V) 820pF 1 10k 2 3 2.3k 4 5 33k +1F 33k +1F 330 3.9k 330 120H 100 9.1k V0- (-5V) + + V0+ (+12V) 120H 0.1F 33k 6 7 8 11 10 9 16k MB3775 13 12 33k + 1.9k 0.1F 15 14 56H 16 0.1F + + 120H 470 0.1F 6 33k 7 8 11 10 9 MB3775 13 12 1.9k 0.1F 33k + 16 0.1F 15 14 56H
220F
220F GND
220F V0+ (+5V)
220F
220F GND
220F
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APPLICATION CIRCUIT (Continued)
Fig. 3 - Chopper Type Step Up/Inverting (For High Speed) 820pF 1 10k 2 2.3k 3 4 33k +1F 33k +1F 220 470 470 120H 9.1k V0- (-5V) + GND + 470 1F 33k 33k + V0+ (+12V) 330pF 150 120H 470 5 0.1F 33k 6 7 8 11 33k 10 9 16k 220F MB3775 15 14 13 12 0.1F + 1.9k 56H 16 0.1F VIN (5V)
220F
220F
Fig. 4 - Multi Output Type (Apply Transformer) 820pF 1 10k 2 3 4 5 6 7 8 MB3775 15 14 13 0.1F 12 33k 11 33k 10 220 9 + 1.8k 1nF 1.9k 16 0.1F 5.6K 0.1F 56H VIN (10V)
220F
-
+
-
+
-
+
-
+
220F
220F
220F
220F
V02(-12V)
V01(-5V)
GND
V02+ (+5V)
V01+ (+12V)
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HOW TO SET OUTPUT VOLTAGE
The output voltage is set using the connection shown in Fig. 5 and 6. The error amplifiers are supplied to the internal reference voltage circuit as are the other internal circuits. The common-mode input voltage range is from -0.2 V to +1.45 V. When the amplifiers are operated non-inverting, tie the inverting terminal to VREF ( are operated inverting, tie the non-inverting terminal to ground.
Fig. 5 -Connection of Error Amp. Output Voltage V0 is plus R2 V0+ [V0+ = VREF X (1 + R2/R1)]
1.28 V). When the amplifiers
+ PIN 5 or PIN 12 R1 -
VREF
Fig. 6 -Connection of Error Amp. Output Voltage V0 is minus R2 V0- [V0- = -VREF X (R2/R1)]
PIN 5 or PIN 12 R1 +
VREF
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HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT PROTECTION CIRCUIT
TIMING CHART shows the configuration of the protection latch circuit. Error amplifier outputs, are internally connected to the non-inverting inputs of the short-circuit protection comparator and are compared with the reference voltage (1.1 V) connected to the inverting input. When the load condition of the switching regulator is stable, the error amplifier has no output fluctuation. Thus, short-circuit protection control is also kept in balance, and the protection enable terminal (pin 15) voltage is kept at about 50 mV. If the load condition drastically changes due to a load short-circuit and if low-level signals (1.1 V or lower) are input to the noninverting inputs of the short-circuit protection comparator from the error amplifiers, the short-circuit protection comparator outputs a "Low" level to turn transistor Q1 off. The protection enable terminal voltage is discharged, and then the short-circuit protection comparator charges the externally connected protection enable capacitor CPE according to the following formula: VPE = 50 mV + tPE x 10-6/CPE 0.65 = 50 mV + tPE x 10-6/CPE CPE = tPE/0.6 (F) When the protection enable capacitor charges to about 0.65 V, the protection latch is set to enable the under voltage lockout protection circuit and to turn the output drive transistor off. The dead time is set to 100 %. Once the under voltage lockout protection circuit is enabled, the protection enable is released; however, the protection latch is not reset if the power is not turned off. The non-inverting inputs of the D.T.C. comparator are connected to the D.T.C. terminals (pins 6 and 11) through the power supply (about 0.9 V) and are compared with a reference voltage (about 1.8 V) connected to the inverting input. To prevent malfunction of the short protection circuit in soft-start mode (using D.T.C. terminals), the D.T.C. comparator outputs a "High" level to turn Q2 on until the D.T.C. terminal voltage drops to about 0.9 V.
Fig. 7 - Protection Latch Circuit
2.5V 1A S.C.P.Comp. R1 Error Amp.1 Error Amp.2 1.1V + + 15 CPE Q1 Q2 Q3 S R U.V.L.O.
Latch
+ + D.T.C.Comp. 1.8V
0.9V 0.9V 6 11
D.T.C.1 D.T.C.2
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SYNCHRONIZATION OF ICs
To synchronize MB3775 ICs, first, the specified capacitor and resistor are connected to the CT and RT terminals of the master IC to start self oscillation. Next, 2 V is applied to the RT terminals of the slave ICs to disable the charge/discharge circuit for triangular wave oscillation. Finally, the CT terminals of the master and slave ICs are connected. Instead of applying VRT to the RT terminals, these terminals can be pulled up by a resistor (see resistance indicated by the dashed line in Fig. 8). Select the pull-up resistance Rpull from the formula given below.
VCC Rpull 0.5 x N
Rpull: Pull up Resistor (k) VCC: Power Supply Voltage (V) N: Number of Slave ICs
Fig. 8 - Connection of Master, Slave
VCC MB3775 (MASTER)
Rpull
CT
RT
MB3775 (SLAVE)
VRT 2V
MB3775 (SLAVE)
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TYPICAL PERFORMANCE CHARACTERISTICS
Fig. 9 - Power supply voltage vs. Reference voltage
2.0 Fig. 10 - Power supply voltage vs. Average supply current 2.0 Average supply current I CCa (mA) 5 10 15 Power supply voltage VCC (V) 20
Reference voltage VREF(V)
1.5
1.5
1.0
1.0
0.5
0.5
0
0
5 10 15 Power supply voltage VCC (V)
20
Fig. 11 - Power supply voltage vs. Stand by current 2.0
Fig. 12 - Reference voltage vs. Temp. 1.29
Reference voltage VREF (V) 5 10 15 Power supply voltage VCC (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 Error Amp Max output voltage VOM (V) 20
Stand by current ICCS (mA)
1.5
1.28
1.0
1.27
0.5
1.26
0
1.25 -30
0
30 60 Temp. Ta (5C)
90
Fig. 13 - Collector saturation voltage vs. Sink current
Fig. 14 - Error Amp. Max. output voltage vs. Frequency 3.0
Collector saturation voltage VSAT (V)
2.0
1.0
50
100 150 200 250 300 Sink current lO (mA)
350
0 100 1K 10K 100K Frequency f(Hz) 1M
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TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Fig. 15 - Timing resistor vs. Oscillation Frequency
1M Triangular waveform cycle ( sec) Fig. 16 - Triangular waveform cycle vs. Timing capacitor 103
Timing resistor fOSC (Hz)
100k
102
10k
CT=150pF
101 Timing resistance=15k VCC=6V
1k
CT=1500pF
10
0
CT=15000pF 100 1K 10K 100K 1M Timing resistor RT () Timing resistance=15k VCC=6V 10M 10-1 101 102 103 104 Timing capacitor CT (pF) 105
Fig. 17 - Timing capacitor vs. Triangular waveform Max. Amplitude voltage
Fig. 18 - Frequency vs. Gain/Phase
60 40 Gain 180 Phase (deg)
Triangular waveform Max. Amplitude voltage (V)
2.2 2.0
Gain AV(dB)
1.8
20
90
1.6
0 -20 Phase
0 -90
1.4
1.2 1.0
-40
-180 90 10M
101
102 103 104 Timing capacitor CT (pF) CFB=1F
105
-60 1K
10K
100K Frequency f(Hz)
1M
Fig. 19 - Frequency vs. Gain/Phase (Actual Data)
60
Fig. 20 - Frequency vs. Gain/Phase (Actual Data)
60 CFB=0.1F 180
40
180
40
Gain AV(dB)
Phase (deg)
Gain AV(dB)
Gain 0 Phase
Gain 0 Phase
0
0
-20
-90
-20
-90
-40 -60 100
-180
-40 -60 100
-180
101
102
103 104 105 Frequency f(Hz)
106
107
101
102
103 104 105 Frequency f(Hz)
106
107
Phase (deg)
20
90
20
90
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TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Fig. 21 - Frequency vs. Gain/Phase (Actual Data) 60 CFB=0.01F 40 180
Gain AV (dB)
20 Gain 0 Phase -20
0
-90
-40 -60 100
-180
101
102
103 104 105 Frequency f(Hz)
106
107
14
Phase (deg)
90
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APPLICATION
1. How to set the error amplifier frequency characteristic
Figure 22 shows the equivalent circuit of the error amplifier. The frequency characteristic of the error amplifier is set by R1, R2, and CP . The high-frequency gain is set by the ratio of resistors 0 dB). R1 and R2 in the IC (set value When CP = 0.1 F, the gain at 20 kHz f 5 MHz is about 0 dB. The roll-off frequency is adjusted by changing external phase compensating capacitor CP (see Fig. 24). When high frequency gain is needed or the phase must be advanced at a low frequency, connect a resistor RP between the FB terminal and CP as shown in Figure 23 (see Fig. 25).
Fig. 22 - Error Amp. Equivalent Circuit Error Amp.
[- IN]
R1 38 k x 120 PWM COMP R2 470
[+ IN]
+
[FB]
CP
Fig. 23 - Error Amp. Equivalent Circuit (Insert RP) Error Amp. [- IN]
R1 38 k x 120 PWM COMP R2 470
[+ IN]
+
[FB]
RP CP
NOTE: As shown above, the frequency characteristic of the error amplifier is set by the external phase compensating capacitor CP . When a ceramic chip capacitor must be used to meet the requirements of a small system, be careful of its temperature . . . . characteristic. (-30 C = 1/5 and 80 C = 1/3 for the frequency characteristic, so a sufficient phase margin must be allowed for at room temperature.) Ceramic chip capacitors with a low temperature characteristic (B characteristic) or film capacitors are recommended (see Fig. 26 to 28).
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Fig. 24 - Error Amp. Frequency characteristics
60 AV 40 (Large) 20 0 (Small) 0 (Small) 90 Phase (deg) Phase (deg) CP=0.1F 180
Gain AV (dB)
-20
(Large)
-90 CP=0.1F -180
-40
-60 10
100
1k
10k
100k
1M
10M
100M
Frequency f(Hz)
Fig. 25 - Error Amp. Frequency characteristics
60 CP=0.1F AV 40 180
20 Gain AV (dB) 0 RP=0 (Large) (Large)
90
0
-20 RP=0 -40
-90
-180
-60 10
100
1k
10k
100k
1M
10M
100M
Frequency f(Hz)
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MB3775
Fig. 26 - Ceramic Chip Capacitor (0.1 F)
20 Temp. characteristic Temp. : Ratio -30C : 0.19 25C : 1.0 80C : 0.32 -30C 0 AV -10 80C 25C -90 -20 1K 10K Frequency f(Hz) 100K 1M 0
90 Phase (deg) -30C 25C 80C Phase (deg) Phase (deg)
10 Gain AV (dB)
Fig. 27 - Tantal Capacitor (0.33 F)
20 Temp. characteristic Temp. : Ratio -30C : 0.95 to 1.05 25C : 1.0 80C : 0.95 to 1.05 AV -30C 25C -10 80C -30C -20 80C 1K 10K Frequency f(Hz) 100K 25C 1M -90
90
10 Gain AV (dB)
0
0
Fig. 28 - Film Capacitor (0.1 F)
20 AV Temp. characteristic -30C : 0.9 to 1.1 25C : 1.0 80C : 0.9 to 1.1 90
10 Gain AV (dB)
0 -30C, 25C, 80C -10
0
-90 -20 1K 10K -30C, 25C 80C Frequency f(Hz) 100K 1M
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MB3775
2. Effect of equivalent series resistance of smoothing capacitor
The equivalent series resistance (ESR) of the smoothing capacitor in the DC/DC converter greatly affects the loop phase characteristic. A smoothing capacitor with a low ESR reduces system stability by increasing the phase shift in the high-frequency region (see Fig. 30). Therefore, a smoothing capacitor with a high ESR will improve system stability. Be careful when using low ESR semiconductor electrolytic capacitors (OS-CON) and tantalum capacitors.
Fig. 29 - Step Down DC/DC Converter Basic Circuit
L Tr RC VIN D C RL
Fig. 30 - Gain vs. Frequency
Fig. 31 - Phase vs. Frequency
20
0
Gain A V (dB)
Phase (deg)
0
(2) -90
-20 (2) -40 (1) : RC=0 (2) : RC=31m -60 10 100 1K Frequency f(Hz) (1) 10K 100K
(1) : RC=0 (2) : RC=31m -180 10 100 1K Frequency f(Hz) 10K
(1)
100K
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MB3775
Reference data If an aluminum electrolytic smoothing capacitor (RC 1.0) is replaced with a low ESR semiconductor electrolytic capacitor (OS-CON: RC 0.2 ), the phase shift is reduced by half (see Fig. 33 and 34).
Fig. 32 - DC/DC Converter AV vs. characteristic Test Circuit VOUT V0+
AV vs. characteristic Between this point. + IN FB + - IN R1 0.1F VREF Error Amp. R2 VIN
~
Fig. 33 - DC/DC Converter +5 V output 60 40 AV Gain A V (dB) 20 0 -20 -40 10 62 VCC=10V RL=25 CP=0.1F 180 V0+ 90 0 Phase (deg) AI Capacitor 22F(16V) - RC 0.2 : fosc=1kHz +
-90 -180 100 1K Frequency f(Hz) 10K 100K
GND
Fig. 34 - DC/DC Converter +5 V output 60 40 Gain A V (dB) 20 0 -20 -40 10 AV VCC=10V RL=25 CP=0.1F 27 180 Phase (deg) 90 0 + V0+ OS-CON 220F(16V) - RC 1.0 : fosc=1KHz
-90 -180 100 1K Frequency f(Hz) 10K 100K
GND
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MB3775
3. Measures for ensuring system stability when a low ESR smoothing capacitor is used
When a low ESR smoothing capacitor is used in the DC/DC converter, only the L and C are apparent even in the high-frequency region, and the phase is delayed by almost 1805. Consequently, the system phase margin and stability are reduced. On the other hand, a low ESR capacitor is needed to reduce the amount of output ripple. This is contrary to the system stability explained above. To solve this problem, phase compensation can be used. This method increases the phase margin by advancing the phase when the phase margin is reduced by a low ESR capacitor. The three suggestions listed below are recommended for DC/DC converters using the MB3775. (1) As shown in Fig. 35, a capacitor is connected in parallel with the output feedback resistor to advance the phase. Use the formula below as a guideline for the capacitance.
C1
1 2fR2 Unstable Frequency (See Fig. 32)
Fig. 35 - External circuit example1 to advance the phase C1
V0+ R2 + IN + - IN R1 CP VREF FB
Fig. 36 - DC/DC Converter +5 V output 60
40
AV 66
180 Phase (deg)
Gain AV (dB)
20 VCC=10V RL=25 CP=0.1F Smoothing Capacitor 22F OS-CON C1=4700pF R1=1.8k R2=5.6 100 1K Frequency f(Hz)
90
0
0
-20
-90
-40 10
-180 10K 100K
20
MB3775
3. Measures for ensuring system stability when a low ESR smoothing capacitor is used (Continued)
(2) As shown in Figure 37, a resistor (RP) is connected between the FB terminal and CP of the error amplifier to advance the phase. The more RP is increased, the more the phase is advanced. However, the gain in the high-frequency range is also increased, which causes instability. Therefore, select the optimum resistance (see Fig. 38).
Fig. 37 - External circuit example 2 to advance the phase V0+ R2 + IN + - IN R1 RP CP VREF FB
Fig. 38 - DC/DC Converter +5 V output 60
40 AV Gain A V (dB) 20 VCC=10V RL=25 CP=0.1F Smoothing Capacitor 22F OS-CON RP=470 R1=1.8k R2=5.6 100 1K Frequency f(Hz) 10K
180 Phase (deg)
45
90
0
0
-20
-90
-40 10
-180 100K
21
MB3775
(3) As shown in Fig. 39, the phase is advanced by using both example 1 and 2 (Fig. 35 and 37).
Fig. 39 - External circuit example 3 to advance the phase C1
V0+ R2 + IN + - IN R1 RP CP VREF FB
4. Error amplifier input ripple voltage
The boost circuit for charging the phase compensating capacitor CP is connected to the error amplifier as shown in Figure 40 to protect against output voltage overload at power-on. A 15 mV offset voltage is provided for the negative input side so that the boost circuit only operates at power-on. When a capacitor is connected in parallel with the output feedback resistor, because the output ripple is too large or for advanced phase compensation, the boost circuit starts operating, which may degrade regulation if the differential input voltage of the error amplifier exceeds 15 mV. Be careful with the differential input voltage of the error amplifier.
Fig. 40 - Error Amp. /Boost Equivalent circuit V0 + VCC
+ Advanced phase compensation capacitor Boost circuit R4
15mV [+ IN] + [- IN] x 120 R2 R3 [FB] CP VREF 470 Error Amp. R1 38 k
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s
PACKAGE DIMENSIONS
16 pins, Plastic DIP (DIP-16P-M04)
19.55 -0.30 .770 -.012
+.008
+0.20
INDEX-1 INDEX-2 6.200.25 (.244.010)
4.36(.172)MAX
0.51(.020)MIN 0.250.05 (.010.002)
3.00(.118)MIN
0.460.08 (.018.003)
+0.30 +.012 +0.30 +.012
0.99 -0 1.27(.050) MAX
1.52 -0
.039 -0
.060 -0 2.54(.100) TYP
7.62(.300) TYP
15MAX
C
1994 FUJITSU LIMITED D16033S-2C-3
Dimensions in mm (inches).
16 pins, Plastic SOP (FPT-16P-M06)
10.15 -0.20 .400 -.008
+0.25 +.010
2.25(.089)MAX 0.05(.002)MIN (STAND OFF)
INDEX
5.300.30 (.209.012) "B"
7.800.40 (.307.016)
6.80 -0.20 +.016 .268 -.008
+0.40
1.27(.050) TYP
0.450.10 (.018.004)
O0.13(.005)
M
0.15 -0.02 +.002 .006 -.001 Details of "A" part 0.40(.016)
+0.05
0.500.20 (.020.008)
Details of "B" part 0.15(.006) 0.20(.008)
"A" 0.10(.004) 8.89(.350)REF
0.20(.008) 0.18(.007)MAX 0.68(.027)MAX 0.18(.007)MAX 0.68(.027)MAX
C
1994 FUJITSU LIMITED F16015S-2C-4
Dimensions in mm (inches).
23
MB3775
16 pins, Plastic SOP (FPT-16P-M05)
* 5.000.10(.197.004)
1.25 -0.10 +.008 .049 -.004
+0.20
0.10(.004)
INDEX
*4.400.10
(.173.004)
6.400.20 (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 -0.05 +.004 .009 -.002
+0.10
"A"
0.15 -0.02 +.002 .006 -.001
+0.05
Details of "A" part 0.100.10(.004.004) (STAND OFF)
4.55(.179)REF
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F16013S-2C-4
Dimensions in mm (inches).
24
MB3775
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9803 (c) FUJITSU LIMITED Printed in Japan
25

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